This project focuses on the design, implementation, and validation of a custom Application-Specific Integrated Circuit (ASIC) for radar signal processing, called the Radar ASIC Waveform Receiver (RAWR). The system is designed to process raw radar data from a Frequency Modulated Continuous Wave (FMCW) radar and convert it into Range-Doppler Maps, which provide critical information about the distance and velocity of objects.

The motivation for this work stems from the limitations of existing FPGA and CPU-based radar processing solutions, which suffer from high power consumption, large physical footprint, and high unit cost. In contrast, the proposed ASIC aims to deliver a compact, low-power, and efficient alternative suitable for embedded applications such as autonomous vehicles, drones, and robotics.

The project integrates four key components: a modified radar frontend to capture raw data, a high-level reference model for verification, a custom ASIC implementing the core digital signal processing pipeline (including windowing and FFT operations), and a validation platform for testing and deployment. The ASIC leverages a time-multiplexed FFT architecture to balance performance and silicon area constraints while maintaining real-time processing capability.